This invention relates to an improved circuit for controlling the sense amplifiers in a semiconductor memory.
A semiconductor memory has a memory cell array comprising a grid of bit lines and word lines, with memory cells disposed at intersections of the bit lines and word lines. When data are read from the memory cells, sense amplifiers amplify potential differences between pairs of bit lines, thereby enabling data stored in the memory cells to be transferred to input/output circuits. Each sense amplifier is coupled to a pair of nodes which are in turn coupled through control transistors to power-supply and ground potentials. Control of the sense amplifiers consists in turning the control transistors on when the memory is accessed and off at other times.
One conventional sense amplifier control circuit has a single control transistor for the power-supply potential and a single control transistor for the ground potential. Each control transistor is coupled by a long supply line to the appropriate sense-amplifier nodes. One resulting problem is that all sense-amplifier current is channeled through a single point on the power-supply side and a single point on the ground side; the sizable current flow at these points leads to significant power-supply and ground noise. Another problem is that parasitic resistance on the long supply lines slows the operation of sense amplifiers that are distant from the control transistors. If the supply lines are widened to reduce the parasitic resistance, however, they take up too much space in the memory device.
In another conventional design the memory cell array is divided into sections, each having a pair of control transistors through which the nodes of sense amplifiers in the section are coupled to the power supply and ground. The control transistors are disposed in word-line shunt areas. This arrangement reduces the parasitic resistance of the supply lines, and reduces power-supply and ground noise, but introduces a new problem: the control transistors on the ground side (or power-supply side) are all driven by a single signal line; now it is the parasitic resistance of this long, heavily-loaded signal line that slows the operation of the sense amplifiers. In addition, space in the word-line shunt areas is limited, which restricts the gate width, hence the current-handling ability, of the control transistors. The narrow gate width of the control transistors becomes another factor limiting the speed of operation.
In yet another conventional design, each sense amplifier has its own pair of control transistors. The total gate width of the control transistors now provides adequate current-handling capability, but the parasitic resistance of the long, heavily-loaded signal lines that control the control transistors is still a problem. In addition, although the total gate width of the control transistors may be large, the gate of each individual control transistor is so small that narrow-channel effects become evident, and variability in the fabrication process can significantly affect transistor characteristics. Under these conditions it is difficult to optimize the dimensions of the control transistors.